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Larry Loeb
Larry Loeb
Larry Loeb

Boosted Rowhammer & Cache Attacks Spell Bad News for Intel

Researchers from Worcester Polytechnic Institute in Massachusetts and the University of Lubeck in Germany have published a paper that is really bad news for Intel.

Researchers from Worcester Polytechnic Institute in Massachusetts and the University of Lübeck in Germany have published a paper, "SPOILER: Speculative Load Hazards Boost Rowhammer and Cache Attacks," that is really bad news for Intel.

It outlines an attack similar to that of Spectre and Meltdown in that it is based the results of speculative execution in a CPU, but on a different set of registers than the first ones use. Here, the Memory Order Buffer is targeted. The MOB is coupled with a CPU cache to manage memory operations.

The researchers found that only Intel CPU chips are vulnerable to this attack. Arm and AMD CPUs are not affected.

The dependency resolution logic that serves the speculative load in the CPU can be exploited to gain information about the physical page mappings that are associated with that load. This is what Rowhammer and cache attacks do in order to obtain a reverse engineering of the virtual-to-physical address mapping.

Worse for Intel, they improved the Rowhammer attack by showing how SPOILER -- the name they gave this class of attack -- helps to conduct DRAM row conflicts deterministically with up to 100% chance, and by demonstrating a double-sided Rowhammer attack with normal user's privilege.

Intel uses a proprietary memory disambiguation and dependency resolution logic in the processors to predict and resolve false dependencies that are related to the speculative load. This makes the speculation results happen faster by not wasting time on intermediate results.

The researchers discovered a false dependency in this process that happens during the 1 MB aliasing of speculative memory accesses which is exploited to leak information about physical page mappings. They note in their paper that, "The leakage can be exploited by a limited set of instructions, which is visible in all Intel generations starting from the1st generation of Intel Core processors, independent of the OS and also works from within virtual machines and sandboxed environments."

So, the root cause for SPOILER is a weakness in the address speculation of Intel's proprietary implementation of the memory subsystem which directly leaks timing behavior due to physical address conflicts.

Oh man, that is a total loss for Intel.

It will make Rowhammer and cache attacks easier, as well as making JavaScript-enabled attacks more feasible.

Mitigation solutions already worked out for Spectre and Meltdown won't work for SPOILER, even though they are both side-channel types of attacks.

The researchers also state that, "There is no software mitigation that can completely erase this problem... The hardware design for the memory disambiguator may be revised to prevent such physical address leakage, but modifying the speculative behavior may cause performance impacts. For instance, partial address comparison was a design choice for performance. Full address comparison may address this vulnerability, but will also impact performance."

Intel is not panicking yet. In a prepared statement given to The Register, they said, "Intel received notice of this research, and we expect that software can be protected against such issues by employing side channel safe software development practices. This includes avoiding control flows that are dependent on the data of interest. We likewise expect that DRAM modules mitigated against Rowhammer style attacks remain protected."

This isn't done yet, not by a long shot.

— Larry Loeb has written for many of the last century's major "dead tree" computer magazines, having been, among other things, a consulting editor for BYTE magazine and senior editor for the launch of WebWeek.

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