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Meet FPGA: The Tiny, Powerful, Hackable Bit of Silicon at the Heart of IoT

Field-programmable gate arrays are flexible, agile-friendly components that populate many infrastructure and IoT devices - and have recently become the targets of researchers finding vulnerabilities.

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Jon M. Kelley
Jon M. Kelley,
User Rank: Moderator
9/9/2019 | 12:28:12 PM
SRAM vs SPI Flash
At a power on boot, a normal SRAM contains no data.  Back in the previous millennium, some companies made battery backed SRAMs, but they were a short lived kludge that disappeared from the market place when usable flash memories first became available. 

Serial Peripheral Interface (SPI) flash is the type of chip that is typically used to store the initial FPGA load stream, and to load modern FPGAs.  If you were to read the information at Thrangrycay (linked to in above article), you will find the statement "...provide root of trust functionality from a dedicated Serial Peripheral Interface (SPI) flash chip." Unfortunately the FPGA that CISCO chose had no means for decrypting an initial load, so the FPGA load set used an unencrypted bitstream.
User Rank: Apprentice
9/6/2019 | 8:26:17 AM
HDL / Bitstreams and other ramblings
I started reading this article instead of just skimming it when I came across the use of "hardware definition language" as hardware description language is considerably more common in the 21st century.  Calling a bitstream HDL is like calling an ELF binary file assembly language code at best. Bitstreams are incredibly difficult to hack, though not impossible. Machine code for a CPU is easy, bitstreams are a whole different animal, making exploiting FPGAs much more difficult and typically requires completely re-writing the NVM on which the bitstream resides via JTAG or some other means. Specialized hardware is almost always required to exploit an FPGA, except in the increasingly common scenarios where USB to JTAG interfaces are put on the product itself just as they are on many developer kits.

FPGA experts are not common. Care needs to be taken in not only the development of the HDL but also the electronic circuit design around the FPGA to harden a system. Careless HDL developers using reference hardware designs from FPGA manufactureres will result in many more exploits akin to those found to date. 

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