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Intel's 9th Gen Processors Offer Protections Against Spectre & Meltdown

While talking up its 9th Gen processors this week, Intel offer some subtle hints about plans to protect its CPUs against the Spectre and Meltdown vulnerabilities that have plague x86 processors.

Larry Loeb

October 12, 2018

3 Min Read

When the Spectre and Meltdown class of vulnerabilities in x86 processors became widely known in March of 2018, the then-CEO of Intel, Brian Krzanich, told the world that its upcoming CPUs would have hardware partitioning enabled for protection.

At this week's Fall Desktop Event, Intel announced just what it was that the company was going to do.

One of the processors Intel talked about was the new Core i9-9900K that offers eight cores and 16 threads. It is clocked at base frequency of 3.6GHz, which can be boosted up to 5GHz.

Intel additionally announced the 9th Gen Core i5 and Core i7 models. The i7-9700K has eight cores and eight threads, and base 3.6GHz clock speed, which can be boosted to 4.9GHz, while the i5-9600K has six cores and six threads at a base 3.7GHz speed -- which can be boosted up to 4.6GHz.

(Source: Intel)\r\n

(Source: Intel)\r\n

All are based on Intel's existing 14nm process, which has been in use since the Broadwell chips of 2014. All these processors are expected to be released in November.

However, with Intel delaying the truly next-gen 10nm Cannon Lake chips until 2019, this is the hardware approach that will be used until those chips emerge.

Buried in all these announcements and speed calculations, Intel offered some guidance on one section on one slide about what the company will do to minimize the Spectre and Meltdown vulnerabilities as far as CPU hardware solutions go.

That one slide, according to Bleeping Computer, notes:

"The new desktop processors include protections for the security vulnerabilities commonly referred to as "Spectre," "Meltdown" and "L1TF." These protections include a combination of the hardware design changes we announced earlier this year as well as software and microcode updates."

Other security points include:

  • Speculative side channel variant Spectre V2 (Branch Target Injection) = Microcode + Software

  • Speculative side channel variant Meltdown V3 (Rogue Data Cache Load) = Hardware

  • Speculative side channel variant Meltdown V3a (Rogue System Register Read) = Microcode

  • Speculative side channel variant V4 (Speculative Store Bypass) = Microcode + Software

  • Speculative side channel variant L1 Terminal Fault = Hardware

It seems that Intel has designed hardware protection for the L1 Terminal Fault and Meltdown V3 -- but not the V3a variation.

This splitting of hardware and software (in microcode) fixes did not impress some users on a forum.

"They're still having to use software. Software = slowdown. Not a 100% hardware fix. I bet there is zero change in the massive performance hit NVMe and Optane take," one observer wrote in a forum. "The thing is there will now be no way to test a before/after as the new BIOSs are required just to run the new CPUs."

"It would take clocking a 9600K exactly like an 8700K with an unfixed BIOS and comparing…," the post added.

The specifics of what exactly is being done in the chips that were announced has not yet been released by Intel. Until it is, users fear that any Intel solution in microcode will also cause a significant performance hit.

Only when the chips have been released to the public will comparison testing be possible.

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— Larry Loeb has written for many of the last century's major "dead tree" computer magazines, having been, among other things, a consulting editor for BYTE magazine and senior editor for the launch of WebWeek.

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About the Author(s)

Larry Loeb

Blogger, Informationweek

Larry Loeb has written for many of the last century's major "dead tree" computer magazines, having been, among other things, a consulting editor for BYTE magazine and senior editor for the launch of WebWeek. He has written a book on the Secure Electronic Transaction Internet protocol. His latest book has the commercially obligatory title of Hack Proofing XML. He's been online since uucp "bang" addressing (where the world existed relative to !decvax), serving as editor of the Macintosh Exchange on BIX and the VARBusiness Exchange. His first Mac had 128 KB of memory, which was a big step up from his first 1130, which had 4 KB, as did his first 1401. You can e-mail him at [email protected].

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