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8/31/2018
08:05 AM
Larry Loeb
Larry Loeb
Larry Loeb

Exploitable Flaws Found in Trusted Platform Module 2.0

The US Department of Defense uses the TPM as a key element in dealing with security of device identification and authentication, encryption and similar tasks.

Four researchers from the National Security Research Institute of South Korea have figured out (PDF) that there are some exploitable flaws in the Trusted Platform Module 2.0, which has been around since 2013.

The attacks would allow an adversary to reset and forge platform configuration registers (PCR) in the TPM. These registers are supposed to securely hold measurements used for bootstrapping a computer.

Mitigation will undoubtedly require new microcode to be applied to firmware, and such patches are not yet available.

The TPM chip is a tamper-resistant hardware device that is equipped with a random number generator, non-volatile storage, encryption functions and status registers. It is a major component of the integrity measurement chain.

For example, the US Department of Defense uses the TPM as a key element in dealing with security of device identification and authentication, encryption and similar tasks. The department has bought into the concept in a big way.

The problem was found to arise in a change made to how a TPM-based system "sleeps" (limited powering down) from TPM 1.2 to TPM 2.0.

A TPM is supposed to save its state to the non-volatile random access memory (NVRAM) after it causes the computer to sleep and restore the state when it wakes. But the specification does not definitively specify how this should be handled when there is no saved state to be restored.

The upshot is that some platforms can allow software to reset the PCRs and therefore extend their value arbitrarily.

This means that a TPM can reset the supposedly saved PCRs coming out of sleep. This could allow an attacker to replay "good" PCR measurements, which in turn means that the TPM would certify that it's in a clean state even though it's compromised.

Busted.

Geralt via Pixabay
Geralt via Pixabay

However, getting to the point where this is of any practical use to an attacker is hard. The researchers assume that the attacker has already taken control of the system software, including the bootloader and the kernel. That by itself is a major thing for an attacker to accomplish.

The attacker would then be able to obtain "good" PCR values from the event logs, which are recorded during a normal boot process. The TPM exploit would be used to convince the victim system that everything is fine, even though it has been hijacked.

The researchers find that TPM microcode changes will be needed. They reported their results to Intel, Dell, GIGABYTE and ASUS, which are the vendors of the devices they tested and confirmed to be vulnerable. They say that Intel and Dell are in the process of patching their firmware to take corrective action. They also got a CVE (CVE-2018-6622) to track things.

Of course, a user might not allow sleep to occur in the system, which would stop the error condition from happening in the first place. Some platforms have this option.

TPM specs need a revision, too. The 2.0 specs should mandate that the TPM enter failure mode if there is no state to restore. This would make the TPM 2.0 specification consistent with the TPM 1.2 specification.

Yet again, we find that hardware-based problems are a continuing source of security anxiety.

Related posts:

— Larry Loeb has written for many of the last century's major "dead tree" computer magazines, having been, among other things, a consulting editor for BYTE magazine and senior editor for the launch of WebWeek.

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