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Endpoint Security

11/16/2018
08:05 AM
Larry Loeb
Larry Loeb
Larry Loeb
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New Spectre & Meltdown Attacks Show Limits of CPU Vulnerabilities

A group of researchers from Belgium, Austria and the US have uncovered more Spectre and Meltdown flaws in CPU architectures, but their paper also shows the limits of these vulnerabilities in real-world attacks.

The class of CPU side-channel vulnerabilities dubbed Spectre and Meltdown arose suddenly in the early part of this year. These hardware flaws are the result of exception or branch misprediction events that can leave secret-dependent traces in the chip's microarchitectural state.

The style of CPU architecture that allows these vulnerabilities has been in use since 1995. (See MIT Researchers Have a DAWG in the Fight Against Spectre & Meltdown.)

Spectre-style attacks break the isolation between applications that is enforced by CPU memory management. Meltdown-style attacks break the fundamental isolation between user applications and the operating system.

The chip industry has been exceedingly busy trying to fix with ad-hoc defenses -- microcode and software patches -- these vulnerabilities, as well as other variants, which have been obviously broken for decades. (See Intel's 9th Gen Processors Offer Protections Against Spectre & Meltdown .)

However, what has not been done up until now is to try and figure out the underlying problems that make these attacks possible.

In a paper entitled, "A Systematic Evaluation of Transient Execution Attacks and Defenses," nine academics -- including those who first discovered Spectre and Meltdown -- try to perform what they deem "a sound and extensible systematization of transient execution attacks." Rather than concentrate on specific examples of attacks, they attempt to draw a wider perspective on all the possible hardware areas that can be attacked.

The researchers use the term "transient execution attacks" since the attacks focus on the CPU hardware that affects instructions, which are executed transiently: The instructions and operations are first created by the extensions in the CPU pipeline, and then they vanish.

Importantly, the researchers note that "transient execution attacks are not limited to the cache: any microarchitectural state that can be changed and observed can be used."

Most attacks seen thus far have used cache state as the way they infer what is really going on in the CPU. To stress that there are more side-channels than just a cache is an important point the researchers make.

By focusing on the hardware areas one-by-one, the researchers found new kinds of attacks as well as ones that would not work.

As far as Meltdown goes, the ones that worked were Meltdown-BR, which exploits an x86 bound instruction on Intel and AMD CPUs, and Meltdown-PK, which bypasses memory protection keys on Intel CPUs.

The academics also found Meltdown attacks did not work on memory alignment check exceptions, division by zero errors, the supervisor mode access prevention (SMAP) mechanism, out-of-limit segment accesses, invalid opcode exception, and non-executable memory.

Three new Spectre attacks that involve the Pattern History Table mechanism were also found, as well as two new ones that use the Branch Target Buffer as a target. The new attacks were possible on AMD, ARM, and Intel CPUs.

Overall, what the paper presents is not truly earth shattering.

It's more an extension of what has already been observed with more detail and texture given. The way that the researchers look at defenses against these sort of exploits is only theoretical. In the paper, they acknowledge that "we need to think about future defenses carefully and plan to mitigate attacks and variants that are unknown."

Yes, the researchers found seven new kinds of attacks. But that is balanced by the group finding six kinds of attacks that we probably don't have to worry about.

Related posts:

— Larry Loeb has written for many of the last century's major "dead tree" computer magazines, having been, among other things, a consulting editor for BYTE magazine and senior editor for the launch of WebWeek.

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