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Edge Articles

9/5/2019
07:00 AM
Curtis Franklin Jr.
Curtis Franklin Jr.
Edge Features

Meet FPGA: The Tiny, Powerful, Hackable Bit of Silicon at the Heart of IoT

Field-programmable gate arrays are flexible, agile-friendly components that populate many infrastructure and IoT devices - and have recently become the targets of researchers finding vulnerabilities.



Image Credit: elen31 via Adobe Stock
Image Credit: elen31 via Adobe Stock

Crack open many of the appliances that populate network and content delivery stacks and you'll find a lot of processing power — but few CPUs. Instead, you're likely to find a field-programmable gate array (FPGA) providing the single-purpose processing required for the job. FPGAs will be part of Internet of Things (IoT) and infrastructure devices for a long time to come, because they are flexible, quickly redefined, and reasonably priced for the functions they deliver.

FPGAs are similar in some aspects to application-specific integrated circuits (ASICs), application-specific standard parts (ASSPs), and other components designed to perform a specific task with high performance and reliability. FPGAs are often used to deliver specific application functions, like encoding the video stream in a camera or editing deck, providing security functions that begin before applications begin running on an IoT device, or calculating mission-critical parameters for defense applications.

There's a key difference, though, that makes FPGAs both a boon to security professionals and a component that adds to their burden of worry.

That difference is in their ability to be updated. ASICs and most ASSPs contain firmware that is "baked in" at the factory; once programmed, they're frozen in development time. An FPGA, on the other hand, can be reprogrammed each time it's rebooted. An FPGA is a blank slate that can be redefined over and over again. Security professionals should be aware of the unique capabilities and growing catalog of vulnerabilities these blanks slates sitting at the heart of so many of the devices in their midst bring to their orgnizations.

A Fresh Start
In a CPU, the configuration of the chip is established at the chip foundry. Programming governs the movement of bits through the pre-set architecture. In an FPGA, though, the configuration is defined by hardware-definition language (HDL) that's loaded from storage — frequently static random access memory (SRAM) — at device boot time. This means the architecture of the device can be optimized for a particular task — and updated or upgraded as vulnerabilities are discovered or new capabilities are licensed.

The ability to update the FPGA is seen as a positive security step because vulnerabilities can be addressed with new definitions.

FPGAs are growing in popularity among device manufacturers because they fit more easily into an "agile" work process than do ASICs. While ASICs have to be defined in a manufacturing process that can take weeks or months in production quantities, FPGAs are defined by software that can be revised as frequently as releases can be dropped — many times a day during development.

As concerns about security and the ability to be updated have gained priority, FPGAs have become more important in production, as well as development. Analysts at Wiseguyreports.com have predicted that the global FPGA market will grow to $63.05 billion in 2019 and is expected to reach $117.97 billion by 2026. 

Weakness in Strength
The boot process is also where security vulnerabilities can enter the process.

Earlier this year, Jatin Kataria, Richard Housley, and Ang Cui of Red Balloon Security discovered the Thrangrycat vulnerabilities in certain Cisco routers. In these vulnerabilities, which won the 2019 Pwnie Award for the most underhyped research, an attacker can interrupt and hijack the "bitstream" — the sequence of HDL that defines the FPGA in the affected routers during boot.

In the case of the Cisco routers, the FPGA was responsible for the Trust Anchor module (TAm) — a piece of the router that is supposed to guard the device against boot-time exploits. If an attacker has gained root access to the device, they can modify the bitstream to disable the TAm and keep it disabled through subsequent reboots of the system.

On the now-unprotected system, a related code-injection vulnerability, discovered by James Chambers, also of Red Balloon Security, would allow the attacker to steal or redirect data at will, since there's no immediately obvious way for a victim to know that the router is working against them.

Vulnerabilities and Opportunities
Many FPGAs can be partitioned among multiple users, just as CPUs can share workloads from many different users and operating systems. Dennis R. E. Gnad, Jonas Krautter, and Mehdi B. Tahoori of the Karlsruhe Institute of Technology (KIT) have demonstrated a side-channel attack in which one user of an FPGA can "spy" on another by monitoring the minute power fluctuations that occur during different operations on the chip.

One difference between the KIT and Thrangrycat vulnerabilities is that Thrangrycat was demonstrated on FPGAs from Xilinx, while the KIT vulnerabilities were not limited to devices from a single vendor. FPGAs are manufactured by a number of vendors, including Intel, Microsemi, Xilinx, Lattice Semiconductor, Cypress Semiconductor, Texas Instruments, and many more.

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Curtis Franklin Jr. is Senior Editor at Dark Reading. In this role he focuses on product and technology coverage for the publication. In addition he works on audio and video programming for Dark Reading and contributes to activities at Interop ITX, Black Hat, INsecurity, and ... View Full Bio

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MatthewG570
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MatthewG570,
User Rank: Apprentice
9/6/2019 | 8:26:17 AM
HDL / Bitstreams and other ramblings
I started reading this article instead of just skimming it when I came across the use of "hardware definition language" as hardware description language is considerably more common in the 21st century.  Calling a bitstream HDL is like calling an ELF binary file assembly language code at best. Bitstreams are incredibly difficult to hack, though not impossible. Machine code for a CPU is easy, bitstreams are a whole different animal, making exploiting FPGAs much more difficult and typically requires completely re-writing the NVM on which the bitstream resides via JTAG or some other means. Specialized hardware is almost always required to exploit an FPGA, except in the increasingly common scenarios where USB to JTAG interfaces are put on the product itself just as they are on many developer kits.

FPGA experts are not common. Care needs to be taken in not only the development of the HDL but also the electronic circuit design around the FPGA to harden a system. Careless HDL developers using reference hardware designs from FPGA manufactureres will result in many more exploits akin to those found to date. 

 
Jon M. Kelley
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50%
Jon M. Kelley,
User Rank: Moderator
9/9/2019 | 12:28:12 PM
SRAM vs SPI Flash
At a power on boot, a normal SRAM contains no data.  Back in the previous millennium, some companies made battery backed SRAMs, but they were a short lived kludge that disappeared from the market place when usable flash memories first became available. 

Serial Peripheral Interface (SPI) flash is the type of chip that is typically used to store the initial FPGA load stream, and to load modern FPGAs.  If you were to read the information at Thrangrycay (linked to in above article), you will find the statement "...provide root of trust functionality from a dedicated Serial Peripheral Interface (SPI) flash chip." Unfortunately the FPGA that CISCO chose had no means for decrypting an initial load, so the FPGA load set used an unencrypted bitstream.
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